Our Pattern Language

This paper describes a pattern language for parallel programming. The authors first make the point that the software industry must change from a sequential to a parallel approach in order to accommodate the increasing shift to parallel processors. This change does not affect all the programmers equally. Low level programmers, who works at the hardware- software interface needs to master parallel programming, while application programmers only need to be weakly aware of it. I found surprising that they mentioned that application programmers may have little background in computer science, specially knowing that a vast majority of computer science graduate work as application programmer.

The benefits of grouping the patterns into a language is that it gives parallel software architects a conceptual framework that help them organize their understanding of the problem and guide them from the beginning of a design to its realization on a real hardware.
As mentioned in the paper I think some of the computational patterns may even be whole pattern languages of their own. I take the example of Graph algorithms. Graph theory is a large area of computer science and there are many different problems that can be solved using some class of graph algorithms. I do not think that they can all be described in one pattern. There need to be pattern for each of the known graph problem, for which there is a solution that expert takes for granted.

I will really be interested in the Data Locality pattern. I took a class in computer architecture and realized our difficult it is to design cache coherence protocol in multicore systems. I think this is one of the major tasks that low level software for multi-processor platforms must handle. Depending on the underlying cache coherence protocol, the low level software must be implemented appropriately to avoid trashing the caches. In single processor systems, it is very easy to figure out where a line of memory is. It is either in memory, in L1 or L2 cache for systems with 2 levels of caches. I a system with multiple processors, the line can be in any processor's L1/L2 cache or in memory.